Design of a Low Power Low Noise System-on-Chip for ECG Monitoring and Diagnostic

A system-on-chip for the application of Electrocardiogram (ECG) monitoring and diagnostic is proposed in this paper, which includes reference circuit, instrumentation amplifier (IA), band-pass filter (BPF), amplifier stage and successive approximation register analog-to-digital converter (SAR-ADC). The Common-Mode Rejection Ratio (CMRR) of IA is greater than 132.87 dB, total gain of the AFE achieves 62.9 dB, and BPF based on a Small-Gm Operational Transconductance Amplifier (OTA) works in the frequency range of 0.5 Hz to 150 Hz. SAR-ADC achieve the ENOB of 7.5 with low power consumption and decent transition speed. The system with a total power consumption of 334.1uW will be supplied by Lithium-ion battery with a normal voltage at 3.7V, and the total input referred noise is 0.41uV. The fabrication process is AMI 0.6 um. All the schematic designs are simulated in Cadence Virtuoso, and the layout simulation is conducted in Cadence Layout. Index Terms — Current balancing-IA, Small-Gm OTA, Low Drop-out Regulator, SAR-ADC, ECG